Frequency synthesizers are in wide use for a variety of applications. For example, frequency synthesizers are used in radio frequency (RF) systems to generate a local oscillator signal or for direct modulation of a transmission signal. Generally, frequency synthesizers employ a phase-lock loop (PLL) circuit having a voltage controlled oscillator (VCO) and a divider. The VCO output signal is divided according to an integer value and compared with a reference signal. The resulting error signal is filtered and applied to the VCO. The synthesizer resolution is dependent on the bandwidth of the synthesizer.
Unlike integer-based frequency synthesizers, fractional-N frequency synthesizers make the choice of synthesizer resolution independent of bandwidth. Referring to FIG. 1, a typical fractional-N frequency synthesizer 10 includes a phase-frequency detector (PFD, generally phase detector) 14 in communication with a summing node 18, a loop filter 22, a VCO 26, and an integer-based divider 30. The divider 30 is also in communication with an accumulator 34. The accumulator 34 is in communication with a digital to analog converter module (DAC) 38 that is coupled to the summing node 18. Based on the required fractional value F and the divider signal DIV, the accumulator 30 sends a carry out signal CO to the divider 30 to dither the instantaneous divider integer value, resulting in a fractional average divider value. The accumulator 30 also provides a residue signal RES to the DAC 38 which generates an output signal DACOUT. The DAC output signal DACOUT is summed with the phase error signal E to compensate for the periodic structure of the phase error signal E resulting from the phase difference between the divider signal DIV and the reference signal REF.
The “phase interpolation” method described above is limited by the ability of the synthesizer 10 to match the DAC output signal DACOUT and the phase error signal E. FIG. 2 graphically illustrates the signals generated and utilized by the synthesizer 10 of FIG. 1 for a case in which the synthesizer 10 is locked and the average divider value is 4.75. In this example, the carry out signal CO is used to dither the divider integer between 4 and 5. The phase error E resulting from the difference of the reference signal REF and the divider signal DIV is periodic and correlates with the cyclic nature of the divider integer value. The phase error E causes fractional spurs in the synthesizer output spectrum at low sideband frequencies. The residue signal RES from the accumulator 34 “tracks” the phase error E and is used to control the DAC 38 so that the DAC output signal DACOUT compensates for the periodic component of the phase error E. Unfortunately, gain matching the DAC output signal DACOUT and the phase error signal E is difficult because the signals DACOUT, E are generated by separate circuit elements. The gain mismatch occurs in both magnitude and time. Consequently, the typical spurious performance achieved using this method is unacceptable for many high performance RF local oscillator applications.
ΣΔ fractional-N frequency synthesizers achieve improved spurious performance by modulating the divider integer value. Quantization noise realized by dithering the divider integer value is randomized (whitened), and shaped to high frequencies so that it is substantially removed by the loop filter 22. However, shaped quantization noise can dominate at intermediate to high offset frequencies. As a result, low phase-noise frequency synthesizers generally have low closed loop bandwidths. This noise-bandwidth tradeoff is contrary to the goal of increased synthesizer bandwidth for fractional-N frequency synthesizers.
Different approaches have been adopted to reduce the impact of the noise-bandwidth tradeoff. Multiple VCO signal phases or divider output signal phases can be used to reduce the quantization step size. However, the number of phases is limited, for example, by gate delays which can be a significant portion of the period of the VCO signal. Moreover, to generate the multiple phases, either a ring oscillator or a delay lock loop (DLL) is typically used, and special attention must be directed to potential phase mismatches between the signal phases. In another approach a ΣΔ digital to analog converter (ΣΔ DAC) is employed to reduce the effect of DAC nonlinearity. Gain matching the ΣΔ DAC output signal and the phase error signal E is difficult because the signals are generated by separate circuits. In addition, to achieve desirable performance, a high resolution DAC is required. Although wideband phase noise levels can be reduced using this technique, the spurious performance is similar to that obtained using other fractional-N frequency synthesizers.
U.S. Pat. No. 6,130,561 describes another technique in which a hybrid charge pump and PFD structure compensates for the phase error between the divider signal DIV and the reference signal REF. The combination of functions in a single hybrid circuit results in a better gain match between the phase error E and the DAC cancellation signals. However, the hybrid structure does not accommodate the mismatch between discrete elements in the DAC, or between the timing signals in the phase detectors, thus there is incomplete phase error signal cancellation and no significant difference in spurious performance.
Thus there remains a need for a fractional-N frequency synthesizer having improved matching between the cancellation DAC output signal and phase error signal. The present invention satisfies this need and provides additional advantages.